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TRSP(M)5018A
The TRSP (M) 5018A series is a 4-bit microcontroller with a PWM direct drive circuit that can play 4-channel melodies or 4-channel ADPCM. The PWM resolution is 8/10/12 bits. They include a low-cost, high-performance CMOS microprocessor. The clock frequency for this uplink is typically 8.192 (±3%) MHz. The chip operates in a wide voltage range of 2.0V ~ 5.5V, and contains program ROM (PROM) and data ROM (DROM).
The maximum program ROM is 4K words and the maximum data ROM size is 56K bytes. The maximum working SRAM is (64+2) half bytes. It provides a total of four software-programmable I/O ports.
The maximum program ROM is 4K words and the maximum data ROM size is 56K bytes. The maximum working SRAM is (64+2) half bytes. It provides a total of four software-programmable I/O ports.
TRSP(M)5018A Description:
The TRSP (M) 5018A series is a 4-bit microcontroller with a PWM direct drive circuit that can play 4-channel melodies or 4-channel ADPCM. The PWM resolution is 8/10/12 bits. They include a low-cost, high-performance CMOS microprocessor. The clock frequency for this uplink is typically 8.192 (±3%) MHz. The chip operates in a wide voltage range of 2.0V ~ 5.5V, and contains program ROM (PROM) and data ROM (DROM).
The maximum program ROM is 4K words and the maximum data ROM size is 56K bytes. The maximum working SRAM is (64+2) half bytes. It provides a total of four software-programmable I/O ports.
The maximum program ROM is 4K words and the maximum data ROM size is 56K bytes. The maximum working SRAM is (64+2) half bytes. It provides a total of four software-programmable I/O ports.
TRSP(M)5018A Features:
Operating voltage: 2.0V to 5.5V
MCU operating frequency: 8.192MHz
Memory size
MCU operating frequency: 8.192MHz
Memory size
- Program ROM size: 4K* 12-bit OTP type
- Data ROM size: 56K x 8-bit OTP type
-SRAM size: 64 x 4 bits
- User register: 2 x 4 bits
- Data ROM size: 56K x 8-bit OTP type
-SRAM size: 64 x 4 bits
- User register: 2 x 4 bits
Power off mode wake-up function:
-HALT mode Wake up source: Port A can wake up from HALT mode to NORMAL mode and execute the wake up subroutine.
4 input/output pins: Port A can be defined bit by bit as an input or output port.
Triple reset condition:
Triple reset condition:
- Low voltage reset. (LVR=2.0 volts)
- Power-on and reset.
- Watchdog timer overflowed.
- Power-on and reset.
- Watchdog timer overflowed.
An internal interrupt source:
-PWM is interrupted.
Alarm display terminal
- Watchdog timer, which can be enabled/disabled by option.
- The WDT period is 256 x 256 x 16/Fsys. (For the system clock =8.192MHz, the WDT cycle is 0.13 seconds)
- The WDT period is 256 x 256 x 16/Fsys. (For the system clock =8.192MHz, the WDT cycle is 0.13 seconds)
Audio output:
- Support PWM or DAC mode with options.
- Support 8/10/12 bits.
- Support 8/10/12 bits.
Support drop-down resistance 1M, 50K or 220K ohm, low voltage reset options.
Oscillator fuse option ±3%, temperature and voltage compensation.
Support read disable security option (1 bit).
Supports 16 level LVD functions.
Oscillator fuse option ±3%, temperature and voltage compensation.
Support read disable security option (1 bit).
Supports 16 level LVD functions.
TRSP(M)5018A package:
5018A%20yjt.jpg)
TRSP(M)5018A block diagram:
5018A%20kt.jpg)
TRSP(M)5018A Application circuit:
5018A%20YYT1.jpg)
5018A%20YYT2.jpg)
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