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NY8TM52D
NY8TM52D is a touch MCU, NY8TM52D core is built on RISC reduced instruction set architecture, a total of 55 instructions. Chip built-in touch function. NY8TM52D has two sets of timers. Under the dual-clock mechanism, the NY8TM52D can select multiple working modes such as Normal mode, Slow mode, Standby mode and sleep mode to save power consumption and extend battery life.
NY8TM52D Description：
NY8TM52D is an 8-bit microcontroller with MTP as program memory, which is suitable for IO product applications. MTP is a more convenient and efficient development product for program memory. The NY8TM52D core is built on the RISC Reduced instruction set architecture and can be easily edited and controlled, with a total of 55 instructions. Except for a few instructions that require 2 sequences, most instructions can be completed in 1 sequence, allowing users to easily complete different applications with program control. Therefore, it is ideal for a variety of low and medium memory capacity but complex applications.
The NY8TM52D has six elastic bidirectional I/O pins, each with a separate register controlled as an input or output pin. And each I/O pin has additional program-controlled functions such as pull or pull down resistance or Open-Drain output. In addition, for infrared remote control products, NY8TM52D has built-in infrared carrier transmitter with selectable frequency. Four of the I/ OS have touch switch function and can be controlled to touch switch input pin via the register. The NY8TM52D has a built-in voltage comparator, which can also select I/O as voltage input and comparison result output via the register.
The NY8TM52D has two sets of timers, which can be counted at the system frequency as a general timing application or triggered from an external signal. In addition, the NY8TM52D provides three sets of 10-bit resolution PWM outputs and a set of buzzer outputs that can be used to drive motors, leds, or buzzers.
The NY8TM52D uses a dual-clock mechanism, and high or low speed oscillations are input by internal RC oscillations. Under the dual-clock mechanism, the NY8TM52D can choose a variety of working modes such as Normal mode, Slow mode, Standby mode and sleep mode to save power consumption and extend battery life.
In power-saving modes such as Standby mode and sleep mode, there are a variety of events that can trigger an interrupt to wake the NY8TM52D into Normal or Slow mode to deal with emergencies.
The NY8TM52D has six elastic bidirectional I/O pins, each with a separate register controlled as an input or output pin. And each I/O pin has additional program-controlled functions such as pull or pull down resistance or Open-Drain output. In addition, for infrared remote control products, NY8TM52D has built-in infrared carrier transmitter with selectable frequency. Four of the I/ OS have touch switch function and can be controlled to touch switch input pin via the register. The NY8TM52D has a built-in voltage comparator, which can also select I/O as voltage input and comparison result output via the register.
The NY8TM52D has two sets of timers, which can be counted at the system frequency as a general timing application or triggered from an external signal. In addition, the NY8TM52D provides three sets of 10-bit resolution PWM outputs and a set of buzzer outputs that can be used to drive motors, leds, or buzzers.
The NY8TM52D uses a dual-clock mechanism, and high or low speed oscillations are input by internal RC oscillations. Under the dual-clock mechanism, the NY8TM52D can choose a variety of working modes such as Normal mode, Slow mode, Standby mode and sleep mode to save power consumption and extend battery life.
In power-saving modes such as Standby mode and sleep mode, there are a variety of events that can trigger an interrupt to wake the NY8TM52D into Normal or Slow mode to deal with emergencies.
NY8TM52D Features:
Wide operating voltage:
2.4V ~ 5.5V @ System frequency ≦8MHz.
3.0V ~ 5.5V @ System frequency > 8MHz.
Wide operating temperature: -40°C ~ 85°C.
2Kx14 bits MTP.
128 bytes SRAM.
Six I/O pins (GPIO) and PB[5:0] that can separately control the input and output directions.
PB[3:0] can optionally input using a built-in pull-down resistor.
PB[5:0] can be either pull-up resistor or Open-Drain.
8-layer Stack.
Access data has direct or indirect addressing modes.
A set of 8-bit upper timer (Timer0) contains programmable frequency predivision lines.
A set of 10-bit downcount timers (Timer1) can optionally be loaded repeatedly or counted continuously.
Three 10-bit pulse-width modulated outputs (PWM1/2/3).
A buzzer output (BZ1).
The 38/57KHz infrared carrier frequency can be selected, and the carrier polarity can also be selected according to the data.
Built-in power-on reset circuit (POR).
Built-in low voltage reset (LVR).
Built-in 16. Segment low voltage detection (LVD).
An accurate Voltage Comparator is built in.
Built-in 4-key touch input pin
Built-in watchdog timer (WDT), which can be switched on and off by the program firmware.
Dual clock mechanism, the system can switch between high speed oscillation or low speed oscillation at any time.
High speed oscillation: I_HRC (1~20MHz internal high speed RC oscillation)
Low-speed oscillation: I_LRC (internal 32KHz low-speed RC oscillation)
Four operating modes can be used to adjust current consumption according to system requirements: Normal mode, Slow mode, Standby mode, and sleep mode.
Eight hardware interrupts:
Timer0 The overflow is interrupted.
Timer1 borrow interrupt.
The WDT is interrupted.
Description The change of PB input status is interrupted.
External interrupt input.
Low voltage detection interrupted.
Touch comparator interrupts.
Touch counter overflow interrupted.
Eight wake interrupts for NY8TM52D in Standby mode:
Timer0 The overflow is interrupted.
Timer1 borrow interrupt.
The WDT is interrupted.
Description The change of PB input status is interrupted.
External interrupt input.
Low voltage detection interrupted.
Touch comparator interrupts.
Touch counter overflow interrupted.
NY8TM52D Five wake interrupts in Halt mode:
The WDT is interrupted.
Description The change of PB input status is interrupted.
External interrupt input.
Touch comparator interrupts.
Touch counter overflow interrupted.
NY8TM52D offers two current levels (Normal/Large)
2.4V ~ 5.5V @ System frequency ≦8MHz.
3.0V ~ 5.5V @ System frequency > 8MHz.
Wide operating temperature: -40°C ~ 85°C.
2Kx14 bits MTP.
128 bytes SRAM.
Six I/O pins (GPIO) and PB[5:0] that can separately control the input and output directions.
PB[3:0] can optionally input using a built-in pull-down resistor.
PB[5:0] can be either pull-up resistor or Open-Drain.
8-layer Stack.
Access data has direct or indirect addressing modes.
A set of 8-bit upper timer (Timer0) contains programmable frequency predivision lines.
A set of 10-bit downcount timers (Timer1) can optionally be loaded repeatedly or counted continuously.
Three 10-bit pulse-width modulated outputs (PWM1/2/3).
A buzzer output (BZ1).
The 38/57KHz infrared carrier frequency can be selected, and the carrier polarity can also be selected according to the data.
Built-in power-on reset circuit (POR).
Built-in low voltage reset (LVR).
Built-in 16. Segment low voltage detection (LVD).
An accurate Voltage Comparator is built in.
Built-in 4-key touch input pin
Built-in watchdog timer (WDT), which can be switched on and off by the program firmware.
Dual clock mechanism, the system can switch between high speed oscillation or low speed oscillation at any time.
High speed oscillation: I_HRC (1~20MHz internal high speed RC oscillation)
Low-speed oscillation: I_LRC (internal 32KHz low-speed RC oscillation)
Four operating modes can be used to adjust current consumption according to system requirements: Normal mode, Slow mode, Standby mode, and sleep mode.
Eight hardware interrupts:
Timer0 The overflow is interrupted.
Timer1 borrow interrupt.
The WDT is interrupted.
Description The change of PB input status is interrupted.
External interrupt input.
Low voltage detection interrupted.
Touch comparator interrupts.
Touch counter overflow interrupted.
Eight wake interrupts for NY8TM52D in Standby mode:
Timer0 The overflow is interrupted.
Timer1 borrow interrupt.
The WDT is interrupted.
Description The change of PB input status is interrupted.
External interrupt input.
Low voltage detection interrupted.
Touch comparator interrupts.
Touch counter overflow interrupted.
NY8TM52D Five wake interrupts in Halt mode:
The WDT is interrupted.
Description The change of PB input status is interrupted.
External interrupt input.
Touch comparator interrupts.
Touch counter overflow interrupted.
NY8TM52D offers two current levels (Normal/Large)
NY8TM52D Block Diagram：
NY8TM52D .
Pin Assignment
NY8TM52D provides three kinds of package type which are SOP8, DIP8 and SOT23-6.
NY8TM52D Pin Description:
Memory Organization:
NY8TM52D memory is divided into two categories: one is program memory and the other is data memory. Data memory is sub-divided into SRAM/Register Memory.
Program Memory:
NY8TM52D Pin Description:
Memory Organization:
NY8TM52D memory is divided into two categories: one is program memory and the other is data memory. Data memory is sub-divided into SRAM/Register Memory.
The program memory space of NY8TM52D is 2K words. Therefore, the Program Counter (PC) is 11-bit wide in order to address any location of program memory.
Some locations of program memory are reserved as interrupt entrance. Power-On Reset vector is located at 0x000. Software interrupt vector is located at 0x001. Internal and external hardware interrupt vector is located at 0x008.
NY8TM52D provides instruction GOTOA, CALLA to address 256 location of program space. NY8TM52D also provides instructions LCALL and LGOTO to address any location of program space.
When a call or interrupt is happening, next ROM address is written to top of the stack, when RET, RETIA or RETIE instruction is executed, the top of stack data is read and load to PC.
NY8TM52D program ROM address 0x7FE~0x7FF are reserved space, if user tries to write code in these addresses will get unexpected false functions.
NY8TM52D program ROM address 0x00E~0x00F are preset rolling code can be released and used as normal program space.
SRAM/Register Memory
According to instructions used to access SRAM/register memory, the memory can be divided into three kinds of categories: one is R-page Special-function Register (SFR) + General Purpose Register (GPR), another is F-page SFR, the others are S-page SFR and T-page SFR. GPR are made of SRAM and user can use them to store variables or intermediate results.
R-page data memory is divided into 4 banks and can be accessed directly or indirectly through a SFR register which is File Select Register (FSR). STATUS[7:6] are used as Bank register BK[1:0] to select one bank out of the 4 banks.
R-page register can be divided into addressing mode: direct addressing mode and indirect addressing mode. The indirect addressing mode of data memory access is described in the following graph. This indirect addressing mode is implied by accessing register INDF. The bank selection is determined by STATUS[7:6] and the location selection is from FSR[6:0].
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